1. Field of the Invention
The present invention relates to substrate structures, and, more particularly, to a substrate structure with enhanced reliability and a method of manufacturing the same.
2. Description of the Prior Art
The versatility and high performance electronic products have proved indispensible along with the booming of electronic industries. So far, the techniques are applied in the chip package field including a flip-chip application, such as chip scale package (CSP), direct chip attached (DCA), multi-chip module (MCM) and so on, or integrating 3-D chip stacking to a 3-D IC chip stacking technique.
The conventional semiconductor package of 3D chip stacking provides a through silicon interposer (TSI) having a plurality of through-silicon vias which penetrate the TSI, and one side of the TSI has a redistribution layer (RDL) to facilitate the electrical connection of the RDL to electrode pads of a semiconductor chip having less pad-spacing, and the another side of the TSI is electrically connected to the solder pads of packaging substrate having larger pad-spacing.
As shown in FIG. 1, a conventional substrate structure 1 of TSI has a carrier 10, a first insulating layer 11 formed on the entire surface of the carrier 10, a wiring layer 13 formed on the first insulating layer 11, a second insulating layer 12 formed on the wiring layer 13 and the first insulating layer 11, with a portion of the wiring layer 13 exposed therefrom, and a plurality of conductive elements 14 formed on the wiring layer 13.
FIGS. 1A-1E are top views of the steps of a method of manufacturing the conventional substrate 1 structure of FIG. 1.
As shown in FIGS. 1 and 1A, a carrier 10, such as a silicon wafer, is provided, and a plurality of conductive pads 101 are formed on the carrier 10.
As shown in FIG. 1B, a first insulating layer 11 is formed on the entire surface of the carrier 10, and a portion of a surface of each of the conductive pads 101 is exposed from the first insulating layer 11.
As shown in FIG. 1C, a wiring layer 13, such as RDL, is formed on the first insulating layer 11 and electrically connected to the conductive pad 101.
As shown in FIG. 1D, a second insulating layer 12 is formed on the wiring layer 13 and the first insulating layer 11, and a portion of a surface of the wiring layer 13 is exposed from the second insulating layer 12.
As shown in FIG. 1E, under bump metallurgy (UBM) 15 is formed on the exposed surface of the wiring layer 13, and a conductive element 14 such as a solder bump is disposed on the under bump metallurgy 15.
However, in the substrate structure 1 thus-manufactured the contact surface between the carrier 10 and the first insulating layer 11 is very large, and the difference of coefficient of thermal expansion (CTE) between the two layers is also very large. Therefore, during the thermal cycle it is difficult for the conventional substrate structure 1 to release thermal stress, and warpage of the conventional substrate structure 1 will be caused easily. Since the stress reliability of the conductive element 14 is poor, it is difficult to carry or apply subsequent processes to the conventional substrate structure 1.
Therefore, how to overcome the weakness of the conventional techniques is an important issue.